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Round 1

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 What are the constraints

Upf contents and details

Retention reg working

Isolation cell working

Power state definition (command)

Issues in synthesis

Different types of clock trees

Difference between h tree and mscts

Power dissipation and reduction techniques

Clock gate insertion and mapping

Steps to debug

Crosstalk and electrom migration in detail

Why drc check and what are the different drc checks

Double patterning

Different between hardip and softip

Hardip examples - RAM ROM PLL

Placement validation

Timing issues faced or analyzed in sta

Scripting language proficiency

Significance of fev

Issues in floorplan

Reasons for cell density

Effect of voltage scaling on timing analysis

Via issues in DRC

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Round 2

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 Sanity checks and mostly on netlist check What are combo loops and how to fix it Floorplan guidelines Why macros are placed before standard cell placement Stages of placememt Signoff checks Post floorplan checks Why synthesis Latches or flops. Which are preferred and why Clock gating Power reduction techinques EM and IR
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Round 3

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  Latch using mux – diagram, waveforms and timing eq. along with the explanation Flop using mux – same as above Why latch preferred over flop ·         From the above diagram, it can be seen that flop is the combination of 2 latches. So using flop consumes more power, more area and requires extra timing analysis. ·         Using latch also have some disadvantages. High dynamic power dissipation and more prone to latches. Power dissipation techniques Low power cells Dynamic power dissipation with respect to CMOS working – cap charging and discharging What happens if we reverse pmos and nmos – expl. with values (-ve thld for pmos and +ve thld for nmos) Graph visualization and expl for different regions of pmos and nmos Congestion aware placement happens at which stage in fusion compiler ·         Compile initial opto What all happens at initial_map stage ...
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