Round 3

 

Latch using mux – diagram, waveforms and timing eq. along with the explanation

Flop using mux – same as above

Why latch preferred over flop

·        From the above diagram, it can be seen that flop is the combination of 2 latches. So using flop consumes more power, more area and requires extra timing analysis.

·        Using latch also have some disadvantages. High dynamic power dissipation and more prone to latches.

Power dissipation techniques

Low power cells

Dynamic power dissipation with respect to CMOS working – cap charging and discharging

What happens if we reverse pmos and nmos – expl. with values (-ve thld for pmos and +ve thld for nmos)

Graph visualization and expl for different regions of pmos and nmos

Congestion aware placement happens at which stage in fusion compiler

·        Compile initial opto

What all happens at initial_map stage

What happens at analyze and elaborate stage

What is register retiming

·        Register moves to either before or after the neighboring registers or logic. Basically its changing the structural location of seq elements to improve PPA.

What happens at logic opto stage

Why placement aware synthesis is required – adv

·        More accurate to the area and congestion

ICG placement with respect to net length

·        Placed near to the port to avoid crosstalk and dynamic p.d.

What happens if we use more number of AON cells in the design

·        Dynamic power dissipation

·        Ir drop

·        Pessimistic usage of area

·        Unnecessary timing analysis > results in run time increase

What is dual rail buffer and why is it used

Time borrowing